In NAND flash memories or an input circuit of the controller thereof, a plurality of CMOS inverters connected in parallel are used as an input buffer. With an increasing demand for high speed operation of the input buffer, the effect of a parasitic capacitance such as a junction capacitance at the output node where the drains of PMOS and NMOS transistors which constitute an output circuit are connected has increased to a level so as not to be negligible. That is, it takes time to charge/discharge the junction capacitance when a signal is transferred to the input buffer, and this causes inter-symbol interference that a past signal level interferes with a present signal level. Thus, the signal level tends to deteriorate due to the inter-symbol interference. In general, since NAND flash memories are used in a state where a plurality of NAND flash memory chips are stacked in a multi-chip package (MCP), the above effect is significant when data is transferred from a controller to the NAND flash memory chips.